SPI0 control1 register.
| SPI_MEM_CLK_MODE | SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. |
| SPI_AR_SIZE0_1_SUPPORT_EN | 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. |
| SPI_AW_SIZE0_1_SUPPORT_EN | 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. |
| SPI_AXI_RDATA_BACK_FAST | 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available. |
| SPI_MEM_RRESP_ECC_ERR_EN | 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. |
| SPI_MEM_AR_SPLICE_EN | Set this bit to enable AXI Read Splice-transfer. |
| SPI_MEM_AW_SPLICE_EN | Set this bit to enable AXI Write Splice-transfer. |
| SPI_MEM_RAM0_EN | When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. |
| SPI_MEM_DUAL_RAM_EN | Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. |
| SPI_MEM_FAST_WRITE_EN | Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2. |
| SPI_MEM_RXFIFO_RST | The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. |
| SPI_MEM_TXFIFO_RST | The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. |